Invalid write prevention for STT-MRAM array
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United States of America Patent
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Apr 30, 2013
Grant Date -
Nov 3, 2011
app pub date -
Apr 29, 2010
filing date -
Apr 29, 2010
priority date (Note) -
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Abstract
In a Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) a bit cell array can have a source line substantially parallel to a word line. The source line can be substantially perpendicular to bit lines. A source line control unit includes a common source line driver and a source line selector configured to select individual ones of the source lines. The source line driver and source line selector can be coupled in multiplexed relation. A bit line control unit includes a common bit line driver and a bit line selector in multiplexed relation. The bit line control unit includes a positive channel metal oxide semiconductor (PMOS) element coupled between the common source line driver and bit line select lines and bit lines.
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