Wafer level semiconductor package and fabrication method thereof
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United States of America Patent
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Apr 16, 2013
Grant Date -
Oct 27, 2011
app pub date -
Jun 27, 2010
filing date -
Apr 26, 2010
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Abstract
A wafer level semiconductor package is provided. A warpage control barrier line formed in every package of a single wafer prevents wafer from warping. The changed shape of the interface between a semiconductor chip and a molding layer at the edge of the package disperses stress applied to the outside of the package, and suppress the generation and propagation of crack. The size of the package is reduced to that of the semiconductor, and the thickness of the package is minimized.
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