Circuit and method for controlling a clock synchronizing circuit for low power refresh operation
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United States of America Patent
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Mar 19, 2013
Grant Date -
Nov 10, 2011
app pub date -
Jul 18, 2011
filing date -
Oct 9, 2003
priority date (Note) -
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Abstract
A method and apparatus is provided for idling a clock synchronizing circuit during at least a portion of time during execution of a refresh operation in a memory device. In a memory device receiving an external clock signal, a method and apparatus for executing a refresh operation is provided that includes initiating at least one refresh operation in the memory device, and ceasing generation of an internal clock signal timed with respect to the external clock signal for at least a portion of the time in which at least one refresh operation takes to complete.
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