E/P durability by using a sub-range of a full programming range
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United States of America Patent
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Mar 19, 2013
Grant Date -
Apr 5, 2012
app pub date -
Nov 14, 2011
filing date -
Apr 4, 2008
priority date (Note) -
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Abstract
A NAND Flash memory controller is used to perform an erase operation on a NAND Flash memory chip including to a cell on the NAND Flash memory chip; the cell is configured to store a first number of bits. It is determined whether the erase operation performed on the NAND Flash memory chip is successful. In the event it is determined that the erase operation performed on the NAND Flash memory chip is unsuccessful, the number of bits stored by the cell is reduced from the first number of bits to a second number of bits; the second number of bits is strictly less than the first number of bits.
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