Mold design and semiconductor package
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United States of America Patent
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Mar 19, 2013
Issued Date -
N/A
app pub date -
Sep 25, 2011
filing date -
May 23, 2007
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A chip package includes a carrier having a first and a second major surface. The first major surface includes an active region surrounded by an inactive region. The chip package includes contact pads in the active region for mating with chip contacts of a chip. A support structure is disposed on the inactive region of the first major surface. The support structure forms a dam that surrounds the active region. When a chip or chip stack is mounted in the active region, spacing exists between the dam and the chip or chip stack. The spacing creates convention paths for heat dissipation.
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