Code design and implementation improvements for low density parity check codes for multiple-input multiple-output channels
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United States of America Patent
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Mar 5, 2013
Grant Date -
Jul 29, 2010
app pub date -
Apr 2, 2010
filing date -
Aug 13, 2004
priority date (Note) -
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status (Latency Note)
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Abstract
Methods include configuring M parallel accumulation engines, accumulating a first information bit at a first set of specific parity bit addresses using the accumulation engines, increasing a parity bit address for each member of the first set of specific parity bit addresses by a pre-determined offset for each new information bit, accumulating subsequent information bits at parity bit addresses that are offset from the specific parity bit addresses by a pre-determined offset until an M+1 information bit is reached, accumulating the next M information bits at a second set of specific parity bit addresses using the accumulation engines, increasing a parity bit address for each member of the second set of specific parity bit addresses by the pre-determined offset for each new information bit; and repeating accumulating and increasing the addresses until the information bits are exhausted. Related systems are described.
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- 5 Citation Count
- H03M Class
- 2.97 % this patent is cited more than
- 12 Age
