Parallel test circuit with active devices
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United States of America Patent
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Feb 26, 2013
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N/A
app pub date -
Feb 21, 2008
filing date -
Aug 24, 2007
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Abstract
In accordance with one embodiment of the invention, a system is provided that comprises a first terminal for receiving an input testing signal during operation; a plurality of input/output terminals coupled with the first terminal; wherein the input/output terminals are configured to parallel output respective output testing signals during parallel output operation; wherein the input/output terminals are configured to parallel input testing response signals during parallel input operation from devices under test; and wherein each of the input/output terminals is electrically isolated during operation from the remaining plurality of input/output terminals.
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