Switch-based parallel distributed cache architecture for memory access on reconfigurable computing platforms
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United States of America Patent
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Feb 12, 2013
Grant Date -
Jul 9, 2009
app pub date -
Jan 3, 2008
filing date -
Jan 3, 2008
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Expired
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Abstract
A computing architecture comprises a plurality of processing elements to perform data processing calculations, a plurality of memory elements to store the data processing results, and a reconfigurable interconnect network to couple the processing elements to the memory elements. The reconfigurable interconnect network includes a switching element, a control element, a plurality of processor interface units, a plurality of memory interface units, and a plurality of application control units. In various embodiments, the processing elements and the interconnect network may be implemented in a field-programmable gate array.
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