Reference voltage buffer and method thereof
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
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Jan 29, 2013
Grant Date -
May 31, 2012
app pub date -
Nov 29, 2010
filing date -
Nov 29, 2010
priority date (Note) -
In Force
status (Latency Note)
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Abstract
An apparatus comprises: an OTA (operational trans-conductance amplifier) with a positive input terminal coupled to a reference voltage, a negative input terminal coupled to a feedback node, and an output terminal shunt to a ground node via a shunt capacitor; a resistor coupling the output terminal of the OTA to the feedback node; and a load circuit coupled to the feedback node via a switch controlled by a logical signal, wherein: an impedance of the shunt capacitor is substantially smaller than an input impedance of the load circuit. In an embodiment, the load circuit is a switch capacitor circuit. A corresponding method using an OTA is also provided.
First Claim
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Family

- 15 United States
- 10 France
- 8 Japan
- 7 China
- 5 Korea
- 2 Other
Patent Owner(s)
Patent Owner | Address | |
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REALTEK SEMICONDUCTOR CORP | 2 INNOVATION RD II SCIENCE PARK HSINCHU |
International Classification(s)

- 2010 Application Filing Year
- H03F Class
- 751 Applications Filed
- 484 Patents Issued To-Date
- 64.45 % Issued To-Date
Inventor(s)
Inventor Name | Address | # of filed Patents | Total Citations |
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Lin, Chia-Liang | Fremont, US | 127 | 2564 |
# of filed Patents : 127 Total Citations : 2564 |
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Patent Citation Ranking
- 0 Citation Count
- H03F Class
- 0 % this patent is cited more than
- 12 Age
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Maintenance Fees
Fee | Large entity fee | small entity fee | micro entity fee | due date |
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Fee | Large entity fee | small entity fee | micro entity fee |
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Surcharge after expiration - Late payment is unavoidable | $700.00 | $350.00 | $175.00 |
Surcharge after expiration - Late payment is unintentional | $1,640.00 | $820.00 | $410.00 |
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