Memory devices including semiconductor pillars
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United States of America Patent
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Jan 29, 2013
Grant Date -
May 24, 2012
app pub date -
Jan 30, 2012
filing date -
Oct 10, 2008
priority date (Note) -
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Abstract
One embodiment relates to an integrated circuit that includes a memory array of pillars arranged in rows and columns. The pillars are separated from one another by row trenches and column trenches. The column trenches include a pair of parallel column trenches. A first trench of the pair includes two parallel bit lines coupled to pillars adjacent to the first trench. A second trench of the pair is free of bit lines. Other methods, devices, and systems are also disclosed.
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