Method of fabricating semiconductor device

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United States of America Patent

PATENT NO 8354713
APP PUB NO 20110215398A1
SERIAL NO

13107542

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Abstract

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In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region.

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Patent Owner(s)

Patent OwnerAddress
RENESAS ELECTRONICS CORPORATION2-24 TOYOSU 3-CHOME KOTO-KU TOKYO 135-0061

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Imai, Yasuo Takasaki, JP 48 864
Kobayashi, Masayoshi Takasaki, JP 123 3376
Kubo, Sakae Takasaki, JP 18 484
Kudo, Satoshi Maebashi, JP 77 1564
Nakazawa, Yoshito Takasaki, JP 108 2954
Numazawa, Sumito Takasaki, JP 16 442
Ohnishi, Akihiro Isesaki, JP 20 570
Oishi, Kentaro Takasaki, JP 36 660
Shigematsu, Takashi Takasaki, JP 93 2680
Uesawa, Kozo Sawa-gun, JP 16 442

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