NAND based NMOS NOR flash memory cell, a NAND based NMOS NOR flash memory array, and a method of forming a NAND based NMOS NOR flash memory array
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United States of America Patent
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Jan 1, 2013
Grant Date -
Feb 23, 2012
app pub date -
Oct 25, 2011
filing date -
May 7, 2008
priority date (Note) -
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Abstract
A NOR flash nonvolatile memory or reconfigurable logic device has an array of NOR flash nonvolatile memory circuits that includes charge retaining transistors serially connected in a NAND string such that at least one of the charge retaining transistors functions as a select gate transistor to prevent leakage current through the charge retaining transistors when the charge retaining transistors is not selected for reading. The topmost charge retaining transistor's drain is connected to a bit line parallel to the charge retaining transistors and the bottommost charge retaining transistor's source is connected to a source line and is parallel to the bit line. The charge retaining transistors are programmed and erased with a Fowler-Nordheim tunneling process.
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