Bit line gate transistor structure for a multilevel, dual-sided nonvolatile memory cell NAND flash array
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United States of America Patent
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Dec 18, 2012
Grant Date -
May 20, 2010
app pub date -
Nov 14, 2008
filing date -
Nov 14, 2008
priority date (Note) -
Expired
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Abstract
A nonvolatile memory structure with pairs of serially connected threshold voltage adjustable select transistors connected to the top and optionally to the bottom of NAND series strings of groups of the dual-sided charge-trapping nonvolatile memory cells for controlling connection of the NAND series string to an associated bit line. A first of the threshold voltage adjustable select transistors has its threshold voltage level adjusted to a first threshold voltage level and a second of the threshold voltage adjustable select transistors adjusted to a second threshold voltage level. The pair of serially connected threshold voltage adjustable select transistors is connected to a first of two associated bit lines. The NAND nonvolatile memory strings further is connected to a pair of serially connected threshold voltage adjustable bottom select transistors that is connected to the second associated bit line.
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