High speed latch circuit with metastability trap and filter
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United States of America Patent
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Dec 18, 2012
Grant Date -
Sep 8, 2011
app pub date -
Feb 28, 2011
filing date -
Mar 4, 2010
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A synchronizer constituted of a first and second set of three serially coupled latches coupled to a common clocking signal, the first and the ultimate latch of the first set responsive to a first edge of a common clocking signal and the penultimate latch responsive to an opposing edge of the common clocking signal, the second set being respectively responsive to the respective complementary edges of the clocking signal; an input lead arranged to receive a signal to be synchronized, the input lead coupled to the input of the first latch of the first set and to the input of the first latch of the second set; and a filter arranged to pass the output of each of the first set and the second set responsive to the penultimate latch of the set exhibiting a consistent output for two consecutive opposing edges.
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