Manufacturing method of SOI MOS device eliminating floating body effects

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United States of America Patent

PATENT NO 8324035
APP PUB NO 20120115287A1
SERIAL NO

13128914

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Abstract

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The present invention discloses a manufacturing method of SOI MOS device eliminating floating body effects. The active area of the SOI MOS structure according to the present invention includes a body region, a N-type source region, a N-type drain region, a heavily doped P-type region, wherein the N-type source region comprises a silicide and a buried insulation region and the heavily doped P-type region is located between the silicide and the buried insulation region. The heavily doped P-type region contacts to the silicide, the body region, the buried insulation layer and the shallow trench isolation (STI) structure respectively. The manufacturing method of the device comprises steps of forming a heavily doped P-type region via ion implantation method, forming a metal layer on a part of the surface of the source region, then obtaining a silicide by the heat treatment of the metal layer and the Si material below. The present invention utilizes the silicide and the heavily doped P-type region to form an ohmic contact in order to release the holes accumulated in the body region of SOI MOS device and eliminate SOI MOS floating body effects. Besides, the manufacturing process is simple and can be easily implement. Further, the manufacturing process according to the present invention will not increase chip area and is compatible with conventional CMOS process.

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Patent Owner(s)

Patent OwnerAddress
SHANGHAI INSTITUTE OF MICROSYSTEM AND INFORMATION TECHNOLOGY CHINESE ACADEMY OF SCIENCES200050 NO 865 CHANGNING ROAD SHANGHAI CHANGNING DISTRICT SHANGHAI CITY SHANGHAI CITY 200050

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Chen, Jing Shanghai, CN 545 3366
Huang, Xiaolu Shanghai, CN 39 88
Luo, Jiexin Shanghai, CN 12 18
Wang, Xi Shanghai, CN 356 3114
Wu, Qingqing Shanghai, CN 15 18

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