Memory controllers
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United States of America Patent
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Nov 20, 2012
Grant Date -
Dec 2, 2010
app pub date -
May 25, 2010
filing date -
May 27, 2009
priority date (Note) -
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Abstract
Techniques pertaining the designs of memory controller are disclosed. According to one aspect of the present invention, a memory controller reduces delays in a data strobe signal of a DDR memory relative to a clock signal of a memory controller thereof. In one embodiment, the memory controller employs four IO ports, two inverters, six edge triggers and a multiplexer. By feeding back an inverted clock signal and utilizing the rising and filing edges of the clock signal, the delays in a data strobe signal of a DDR memory relative to a clock signal of a memory controller are considerably reduced or minimized.
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