Integrated memory control apparatus and method thereof
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United States of America Patent
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Nov 6, 2012
Grant Date -
Nov 10, 2011
app pub date -
Jul 22, 2011
filing date -
Sep 6, 2007
priority date (Note) -
Expired
status (Latency Note)
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Abstract
An integrated memory control apparatus including a first interface decoder, a second interface decoder and an interface controller is provided. Wherein, the first interface decoder is coupled to a control chip through a first serial peripheral interface (SPI), the second interface decoder is coupled to a micro-processor unit through a general transmission interface, and the interface controller is coupled to a memory through a second SPI. When the interface controller receives the request signals from the control chip and the micro-processor unit, the control chip may correctly read data from the memory through the first and second SPI. On the other hand, the micro-processor unit may stop reading data from the memory through the general transmission interface. Therefore, the control chip and the micro-processor unit may share the same memory.
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