Low-voltage EEPROM array
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United States of America Patent
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Nov 6, 2012
Grant Date -
Feb 16, 2012
app pub date -
Aug 12, 2010
filing date -
Aug 12, 2010
priority date (Note) -
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Abstract
A low-voltage EEPROM array, which has a plurality of parallel bit lines, parallel word lines and parallel common source lines is disclosed. The bit lines include a first bit line. The word lines include a first word line and a second word line. The common source lines include a first common source line and a second common source line. The low-voltage EEPROM array also has a plurality of sub-memory arrays. Each sub-memory array includes a first memory cell and a second memory cell. The first memory cell connects with the first bit line, the first common source line and the first word line. The second memory cell connects with the first bit line, the second common source line and the second word line. The first and second memory cells are symmetrical and arranged between the first and second common source lines.
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