Semiconductor device having a multilevel interconnect structure and method for fabricating the same
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United States of America Patent
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Nov 6, 2012
Grant Date -
Sep 24, 2009
app pub date -
Mar 19, 2009
filing date -
Mar 19, 2008
priority date (Note) -
Expired
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Abstract
A multilevel interconnect structure in a semiconductor device includes a first insulating layer formed on a semiconductor wafer, a Cu interconnect layer formed on the first insulating layer, a second insulating layer formed on the Cu interconnect layer, and a metal oxide layer formed at an interface between the Cu interconnect layer and the second insulating layer. The metal oxide layer is formed by immersion-plating a metal, such as Sn or Zn, on the Cu interconnect layer and then heat-treating the plated layer in an oxidizing atmosphere.
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