Method of product performance improvement by selective feature sizing of semiconductor devices
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United States of America Patent
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Oct 30, 2012
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N/A
app pub date -
Mar 10, 2009
filing date -
Mar 10, 2009
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Abstract
Device features, such as gate lengths and channel widths, are selectively altered by first identifying those devices within a semiconductor die that exhibit physical attributes, e.g., leakage current and threshold voltage magnitude, that are different than previously verified by a design/simulation tool used to design the devices. The identified, non-conforming devices are then further identified by the amount of deviation from the original design goal that is exhibited by each non-conforming device. The non-conforming devices are then mathematically categorized into bins, where each bin is tagged with a magnitude of deviation from a design goal. The mask layers defining the features of the non-conforming devices are then selectively modified by an amount that is commensurate with the tagged deviation. The selectively modified mask layers are then used to generate a new semiconductor die that exhibits improved performance.
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