Cost saving electrically-erasable-programmable read-only memory (EEPROM) array
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United States of America Patent
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Oct 30, 2012
Grant Date -
Feb 16, 2012
app pub date -
Aug 11, 2010
filing date -
Aug 11, 2010
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Abstract
A cost saving EEPROM array, having: a plurality of parallel bit lines, a plurality of parallel word lines, and a plurality of parallel common source lines. The bit lines contain a first group bit lines; the word line includes a first and a second word lines; and the common source line includes a first common source line. And, a plurality of sub-memory arrays are provided. Each sub-memory array includes a first and a second memory cells disposed opposite to each other and located on two different sides of the first common source line; the first memory cell is connected to the first group bit lines, the first common source line, and the first word line, and the second memory cell is connected to the first group bit line, the first common source line, and the second word line.
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