Dual damascene with amorphous carbon for 3D deep via/trench application
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United States of America Patent
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Oct 30, 2012
Grant Date -
Apr 2, 2009
app pub date -
Sep 28, 2007
filing date -
Sep 28, 2007
priority date (Note) -
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Abstract
A method for fabricating a 3-D monolithic memory device in which a via and trench are etched using an amorphous carbon hard mask. The via extends in multiple levels of the device as a multi-level vertical interconnect. The trench extends laterally, such as to provide a word line or bit line for memory cells, or to provide other routing paths. A dual damascene process can be used in which the via is formed first and the trench is formed second, or the trench is formed first and the via is formed second. The technique is particularly suitable for deep via applications, such as for via depths of greater than 1 μm. A dielectric antireflective coating, optionally with a bottom antireflective coating, can be used to etch an amorphous carbon layer to provide the amorphous carbon hard mask.
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