Cryptographic bus architecture for the prevention of differential power analysis
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United States of America Patent
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Oct 23, 2012
Grant Date -
Dec 8, 2005
app pub date -
Jun 8, 2004
filing date -
Jun 8, 2004
priority date (Note) -
Expired
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Abstract
An apparatus and method for preventing information leakage attacks through a polarized cryptographic bus architecture. The polarized cryptographic bus architecture randomly changes the polarity of the target bit such that the leaked information cannot be consistently averaged to yield statistical key material. Further, to increase the prevention of information leakage attacks, a set of dual rails is used to write data to a given register bit.
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