Method for mitigating adverse processor loading in a personal computer implementation of a wireless local area network adapter

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United States of America Patent

PATENT NO 8296455
APP PUB NO 20080019277A1
SERIAL NO

11839152

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Abstract

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A personal computer's (PC) microprocessor is used to provide both the physical layer (PHY) and media access control (MAC) processing functions required to implement a wireless local area network (WLAN) adapter. This technique uses the polling mechanism associated with the power save (PS) functionality of WLAN protocol to relieve networking stress on the host processing system. It does this while maintaining networking integrity and packet delivery. The WLAN protocol polling mechanism is used to briefly inhibit the transfer of packets from the WLAN access point (AP) during peak periods of network traffic and/or host processor loading. Because the modulation, demodulation, and MAC functions, typically implemented in dedicated hardware on existing adapters are implemented in software running on the host PC microprocessor, other host system processes and applications can interfere with these time critical functions. Conversely, latency introduced by WLAN specific processing tasks during peak periods of network traffic may cause unacceptable delays to the other processes and applications requiring microprocessor attention. In addition to its primary stated purpose of allowing WLAN mobile stations to save power, this technique will use power save polling as a method for controlling delivery of network packets when the host is heavily loaded or when peak interrupt latencies make reliable packet delivery difficult or impossible.

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Patent Owner(s)

Patent OwnerAddress
INTELLECTUAL VENTURES I LLC2711 CENTERVILLE ROAD SUITE 400 WILMINGTON DE 19808

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Hoffmann, John Erich Indialantic, US 11 308
Nelson,, Jr George Rodney Merritt Island, US 23 141
Schultz, Richard Douglas Melbourne, US 16 981

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