Microprocessor with selectively available random number generator based on self-test result
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United States of America Patent
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Oct 23, 2012
Grant Date -
Apr 5, 2007
app pub date -
Dec 16, 2006
filing date -
Nov 20, 2001
priority date (Note) -
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Abstract
A microprocessor including a random number generator within its instruction set architecture and made selectively available to program instructions of the instruction set architecture depending upon results of a self-test of the random number generator performed is disclosed. The microprocessor also includes a self-test unit that performs the self-test in response to a reset. The microprocessor also includes an instruction translator that translates instructions of the instruction set architecture, including instructions related exclusively to operation of the random number generator. The microprocessor generates a fault defined by the instruction set architecture in response to execution of one of the plurality of instructions related exclusively to operation of the random number generator if the self-test unit previously determined the random number generator is not operating properly.
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