Row-decoder and select gate decoder structures suitable for flashed-based EEPROM operating below +/− 10v BVDS
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United States of America Patent
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Oct 23, 2012
Grant Date -
Dec 17, 2009
app pub date -
Jun 16, 2009
filing date -
Jun 16, 2008
priority date (Note) -
Expired
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Abstract
A nonvolatile memory device includes an array of EEPROM configured nonvolatile memory cells each having a floating gate memory transistor for storing a digital datum and a floating gate select transistor for activating the floating gate memory transistor for reading, programming, and erasing. The nonvolatile memory device has a row decoder to transfer the operational biasing voltage levels to word lines connected to the floating gate memory transistors for reading, programming, verifying, and erasing the selected nonvolatile memory cells. The nonvolatile memory device has a select gate decoder circuit transfers select gate control biasing voltages to the select gate control lines connected to the control gate of the floating gate select transistor for reading, programming, verifying, and erasing the floating gate memory transistor of the selected nonvolatile memory cells. The operational biasing voltage levels are generated to minimize operational disturbances and preventing drain to source breakdown in peripheral devices.
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