Apparatus and method for inhibiting excess leakage current in unselected nonvolatile memory cells in an array
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United States of America Patent
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Oct 16, 2012
Grant Date -
Dec 24, 2009
app pub date -
Jun 22, 2009
filing date -
Jun 20, 2008
priority date (Note) -
Expired
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Abstract
An apparatus and method for operating an array of NOR connected flash nonvolatile memory cells erases the array in increments of a page, block, sector, or the entire array while minimizing sub-threshold leakage current through unselected nonvolatile memory cells. The apparatus has a row decoder circuit and a source decoder circuit for selecting the nonvolatile memory cells for providing biasing conditions for reading, programming, verifying, and erasing the selected nonvolatile memory cells while minimizing sub-threshold leakage current through unselected nonvolatile memory cells.
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