Complex analog to digital converter (CADC) system on chip double rate architecture
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Oct 2, 2012
Grant Date -
Apr 5, 2012
app pub date -
Sep 30, 2010
filing date -
Sep 30, 2010
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A Complex Analog to Digital Converter System on Chip (CADC SoC) implemented into a microcircuit system is provided. A series of stagger clock signals can be fixed on either a rising or falling edge of the system clock and a plurality of A/D converters can be grouped by sets (i.e. odd and even) and assigned to odd or even stagger clocks. A complex I&Q data manager is provided for controlling the system. A clock management system is responsive to an external signal to select from a set of stagger clock settings, thereby improving anti-alias performance.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully