Method and apparatus for computing a sliding sum of absolute differences
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United States of America Patent
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Sep 18, 2012
Grant Date -
Aug 12, 2010
app pub date -
Mar 29, 2007
filing date -
Mar 31, 2006
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A logic circuit is configured to calculate a sliding sum of absolute differences of a plurality of numbers from a plurality of members respectively selected successively from all members of a sequence of numbers. The logic circuit reduces an amount of logic that is required to perform the sum of absolute differences, and thereby saves resources and latency.
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