Integrated circuit including doped semiconductor line having conductive cladding
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United States of America Patent
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Aug 28, 2012
Grant Date -
Mar 11, 2010
app pub date -
Sep 8, 2008
filing date -
Oct 31, 2007
priority date (Note) -
Expired
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Abstract
An integrated circuit includes an array of memory cells. Each memory cell includes a diode. The integrated circuit includes a doped semiconductor line formed in a semiconductor substrate. The doped semiconductor line is coupled to a row of diodes. The integrated circuit includes conductive cladding contacting the doped semiconductor line.
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