Turning off buffer when a digital back end operates at a same data rate as the analog front end
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United States of America Patent
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Aug 21, 2012
Grant Date -
Mar 10, 2011
app pub date -
Mar 27, 2008
filing date -
Mar 27, 2008
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A processor circuit having reduced power consumption includes an analog front end operative to receive an analog signal supplied to the processor circuit and to generate a digital signal indicative of the analog signal. The processor further includes a digital back end operative to generate a digital output signal as a function of the digital signal generated by the analog front end. A buffer is coupled between the analog front end and the digital back end. In a first mode of operation, the digital back end operates at a substantially same data rate as the analog front end and the buffer is bypassed. In a second mode of operation, the digital back end operates at a higher data rate than the analog front end and the buffer is used to store outputs of the analog front end.
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