Multilevel cell NAND flash memory storage system, and controller and access method thereof
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United States of America Patent
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Jul 17, 2012
Grant Date -
Aug 12, 2010
app pub date -
Mar 27, 2009
filing date -
Feb 10, 2009
priority date (Note) -
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Abstract
A multi level cell (MLC) NAND flash memory storage system is provided. A controller of the MLC NAND flash memory storage system declares it a signal level cell (SLC) NAND flash memory chip to a host system connected thereto and provides a plurality of SLC logical blocks to the host system. When the controller receives a write command and a user data from the host system, the controller writes the user data into a page of a MLC physical block and records the page of the SLC logical block corresponding to the page of the MLC physical block. When the controller receives an erase command from the host system, the controller writes a predetermined data into the page of the MLC physical block mapped to the SLC logical block to be erased, wherein the predetermined data has the same pattern as a pattern of the erased page.
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