Non-volatile memory low voltage and high speed erasure method
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United States of America Patent
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Jul 10, 2012
Grant Date -
Jul 28, 2011
app pub date -
Jan 25, 2010
filing date -
Jan 25, 2010
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Abstract
A non-volatile memory low voltage and high speed erasure method, the non-volatile memory is realized through disposing a stacked gate structure having a control gate and a floating gate on a semiconductor substrate or in an isolation well, such that adequate hot holes are generated in proceeding with low voltage and high speed erasure operation through a drain reverse bias and making changes to gate voltage. In addition, through applying positive and negative voltages on a drain, a gate, and a semiconductor substrate or well regions, adequate hot holes are generated, so as to lower the absolute voltage in achieving the objective of reducing voltage of erasing memory.
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