Fault tolerant redundant clock circuit
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United States of America Patent
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Jul 10, 2012
Grant Date -
May 27, 2010
app pub date -
Nov 17, 2009
filing date -
Nov 19, 2008
priority date (Note) -
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Abstract
A clock generation circuit, includes, in part, a comparator, a logic unit, and a switching circuit. The switching circuit generates a signal that is applied to the comparator. If the input voltage level of the signal applied to the comparator is greater than a first reference voltage, the comparator asserts its first output signals. If the input voltage level of the signal applied to the comparator is less than a second reference voltage, the comparator asserts its second output signal. The output signals of the comparator form a first pair of feedback signals applied to the switching circuit. The logic unit responds to the output signals of the comparator to generate a second pair of oscillating feedback signals that are also applied to the switching circuit. The switching circuit varies a capacitor voltage in response to a reference current and in response to the two pairs of feedback signals it receives.
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