Method of fabricating a trench power MOS transistor
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United States of America Patent
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Jul 3, 2012
Grant Date -
Apr 26, 2012
app pub date -
Dec 29, 2011
filing date -
Jan 6, 2010
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Abstract
A trench-typed power MOS transistor comprises a trench-typed gate area, which includes a gate conductor and an isolation layer. A thin sidewall region of the isolation layer is formed between the gate conductor and a well region. A thick sidewall region of the isolation layer is formed between the gate conductor and a double diffusion region. A thick bottom region of the isolation layer is formed between the gate conductor and a deep well region.
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