Charge retention structures and techniques for implementing charge controlled resistors in memory cells and arrays of memory
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United States of America Patent
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May 29, 2012
Grant Date -
Jun 17, 2010
app pub date -
Dec 16, 2009
filing date -
Dec 17, 2008
priority date (Note) -
Expired
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Abstract
Embodiments of the invention relate generally to semiconductors and semiconductor fabrication techniques, and more particularly, to devices, integrated circuits, memory cells and arrays, and methods to use silicon carbide structures to retain amounts of charge indicative of a resistive state in, for example, a charge-controlled resistor of a memory cell. In some embodiments, a memory cell comprises a silicon carbide structure including a charge reservoir configured to store an amount of charge carriers constituting a charge cloud. The amount of charge carriers in the charge cloud can represent a data value. Further, the memory cell includes a resistive element in communication with the charge reservoir and is configured to provide a resistance as a function of the amount of charge carriers in the charge reservoir. The charge reservoir is configured to modulate the size of the charge cloud to change the data value.
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