Methods for gate-length biasing using annotation data
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United States of America Patent
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May 22, 2012
Grant Date -
Jul 1, 2010
app pub date -
Mar 4, 2010
filing date -
May 6, 2005
priority date (Note) -
Expired
status (Latency Note)
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Abstract
Methods for generating a biased layout for making an integrated circuit are disclosed. One such method includes obtaining a nominal layout defined by one or more cells, where each cell has one or more transistor gate features with a nominal gate length. Then, obtaining an annotated layout. The annotated layout contains information describing gate-length biasing of one or more of the transistor gate features in one or more cells of the nominal layout. A biased layout is produced by modifying the nominal layout using the information from the annotated layout. The biasing modifies a gate length of those transistor gate features identified by the information of the annotated layout.
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