Semiconductor device and manufacturing method thereof for reducing the area of the memory cell region
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United States of America Patent
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May 22, 2012
Grant Date -
Apr 15, 2010
app pub date -
Dec 11, 2009
filing date -
Oct 7, 2005
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A structure is adopted for a layout of an SRAM cell which provides a local wiring 3a between a gate 2a and gate 2b and connects an active region 1a and an active region 1b. This eliminates the necessity for providing a contact between the gate 2a and the gate 2b. Therefore, it is possible to reduce the size of a memory cell region C in a short side direction. Furthermore, a structure whereby a left end of a gate 2c is retreated from the gate 2a and a local wiring 3b which connects the active region 1b and gate 2c disposed in a diagonal direction is adopted. This allows the gate 2a to be shifted toward the center of the memory cell region C.
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