Clock domain data transfer device and methods thereof
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United States of America Patent
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May 8, 2012
Grant Date -
Oct 22, 2009
app pub date -
Apr 16, 2008
filing date -
Apr 16, 2008
priority date (Note) -
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Abstract
Two clock domains of a data processing device are each synchronized with a different clock signal. The clock signals are generated by clock generation logic. The clock generation logic also generates a transfer enable signal based on the relative frequency of each clock signal to indicate when data can be transferred between the clock domains. Further, as the relative frequency of the clock signals change, the timing of the transfer enable signal also changes to ensure reliable data transfer.
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