Phase lock loop control error selection system and method
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United States of America Patent
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May 8, 2012
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N/A
app pub date -
Oct 30, 2006
filing date -
Jun 30, 2005
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Abstract
In one embodiment, a cross zero best error selection system includes an error input interface, a most significant bit summation component and a multiplexer. The error input interface in coupled to a most significant bit summation component which in turn is coupled to a multiplexer. The error input interface receives a plurality of future error values. The most significant bit summation component sums most significant bits of said future error values. The multiplexer for selects error value based upon said summation of said most significant bits.
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