Level shifter with output spike reduction
Number of patents in Portfolio can not be more than 2000
United States of America
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May 8, 2012
Issued Date -
N/A
app pub date -
Jul 17, 2009
filing date -
Jul 17, 2009
priority date (Note) -
Withdrawn
status (Latency Note)
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Abstract
A level shifter, or method, producing a final output from a driver supplied by a high-side source driver providing VDD or common, and a low-side source driver providing common or VSS. A delay is introduced to prevent a source driver output at common from beginning to transition toward a supply rail until a delaying source driver at a rail begins transitioning toward common. The level shifter may be single-ended or differential, and the delaying source driver may be coupled to the same final output driver as is the delayed source driver, or may be coupled to a different final output driver. The level shifter may have a second level shifter front end stage, which may have high-side and low-side intermediate source driver outputs coupled by a capacitor, and/or may couple one of the supplies to all intermediate source drivers via a common impedance or current limit Zs.
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