Semiconductor package with embedded die
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United States of America Patent
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May 8, 2012
Grant Date -
May 15, 2008
app pub date -
Nov 10, 2006
filing date -
Nov 10, 2006
priority date (Note) -
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Abstract
A semiconductor package having an embedded die and solid vertical interconnections, such as stud bump interconnections, for increased integration in the direction of the z-axis (i.e., in a direction normal to the circuit side of the die). The semiconductor package can include a die mounted in a face-up configuration (similar to a wire bond package) or in a face-down or flip chip configuration.
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