Driving power-supply circuit
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United States of America Patent
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-
May 1, 2012
Grant Date -
Feb 10, 2011
app pub date -
Sep 2, 2010
filing date -
Jul 29, 2005
priority date (Note) -
Expired
status (Latency Note)
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Abstract
The object of the present invention is reducing power consumption of a driving power supply circuit. In the case where the driving voltage Vi is higher than the reference voltage ViH, The signal S3P, S3N of the differential amplifier 30P, 30N become level “L” concurrently, and the signal S4P, S4N of the output circuit 40P, 40N become level “H”. Subsequently, the NMOS 62 becomes on-state and decreases the driving voltage Vi of the node N6. At the above stage, the control signal CP becomes level “L”, then the operation of the constant current circuit 20P is halted.
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