Semiconductor package formed within an encapsulation
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United States of America Patent
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May 1, 2012
Grant Date -
Aug 12, 2010
app pub date -
Apr 15, 2010
filing date -
Nov 23, 2005
priority date (Note) -
Expired
status (Latency Note)
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Abstract
Provided are a semiconductor package which is small in size but includes a large number of terminals disposed at intervals equal to or greater than a minimum pitch, and a method of fabricating the semiconductor package. The semiconductor package includes a semiconductor chip having a bottom surface on which a plurality of bumps are formed, redistribution layer patterns formed under the semiconductor chip and each including a first part electrically connected to at least one of the bumps and a second part electrically connected to the first part, an encapsulation layer surrounding at least a top surface of the semiconductor chip, and a patterned insulating layer formed below the redistribution layer patterns and exposing at least parts of the second parts of the redistribution layer patterns.
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