Chip scale package structure with can attachment
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United States of America Patent
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Apr 24, 2012
Issued Date -
N/A
app pub date -
Dec 16, 2008
filing date -
Dec 16, 2008
priority date (Note) -
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Abstract
A chip scale package (CSP) device includes a CSP having a semiconductor die electrically coupled to a plurality of solder balls. A can having an inside top surface and one or more side walls defines a chamber. The CSP is housed in the chamber and is attached to the inside top surface of the can. A printed circuit board is attached to the solder balls and to the one or more side walls to provide support to the CSP and to the can. The CSP may be a Wafer-Level CSP. The can may be built from a metallic substance or from a non-metallic substance. The can provides stress relief to the CSP during a drop test and during a thermal cycle test.
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