Pad in semicondcutor device and fabricating method thereof
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United States of America Patent
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Apr 17, 2012
Grant Date -
Jul 2, 2009
app pub date -
Nov 21, 2008
filing date -
Dec 26, 2007
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A pad in a semiconductor device and fabricating method thereof are disclosed. The pad includes an uppermost metal layer first to Nth intermediate metal layers, wherein capacitors configured or formed by the uppermost metal layer and the first to Nth intermediate metal layers are serially connected. Accordingly, the pad reduces total parasitic capacitance components by connecting MIM type capacitors in series, and not necessarily overlapping with each other, thereby minimizing design errors attributed to the pad by reducing parasitic factors generated from the integrated circuit design. The pad may also minimize capacitance attributed to resonance at a specific frequency. Moreover, the pad avoids affecting an adjacent pad or circuit without additional processing, despite maintaining the above-mentioned effects, thereby reducing cost.
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