Semiconductor integrated circuit device having a dummy metal wiring line
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United States of America Patent
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Apr 17, 2012
Grant Date -
Jul 29, 2010
app pub date -
Feb 24, 2009
filing date -
Jul 4, 2008
priority date (Note) -
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Abstract
There is provided a layout structure of a semiconductor integrated circuit capable of preventing the thinning of a metal wiring line close to a cell boundary and wire breakage therein without involving increases in the amount of data for OPC correction and OPC process time. In a region interposed between a power supply line and a ground line each placed to extend in a first direction, first and second cells each having a transistor and an intra-cell line each for implementing a circuit function are placed to be adjacent to each other in the first direction. In a boundary portion between the first and second cells, a metal wiring line extending in a second direction orthogonal to the first direction is placed so as not to short-circuit the power supply line and the ground line.
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