Method for optimizing an integrated circuit physical layout
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United States of America Patent
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Apr 3, 2012
Grant Date -
Jun 10, 2010
app pub date -
Jun 27, 2007
filing date -
Jun 27, 2006
priority date (Note) -
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Abstract
The invention relates to a method of optimizing an integrated circuit layout, wherein an initial integrated circuit layout is provided. A predetermined set of physical characteristics of a predetermined set of polygons of said initial circuit layout, is assessed and said physical characteristics are aggregated to derive an integral quality number associated to said initial circuit layout. According to the invention, cost functions are generated to evaluate a perturbed quality number of said perturbed layout and layout perturbations are selected that optimize the quality number, so that the circuit layout is optimized.
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