Memory system having NAND-based NOR and NAND flashes and SRAM integrated in one chip for hybrid data, code and cache storage
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United States of America Patent
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Apr 3, 2012
Grant Date -
Dec 30, 2010
app pub date -
Feb 5, 2010
filing date -
Jun 30, 2009
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A memory system includes a NAND flash memory, a NOR flash memory and a SRAM memory on a single chip. Both NAND and NOR memories are manufactured by the same NAND manufacturing process and NAND cells. The three memories share the same address bus, data bus, and pins of the single chip. The address bus is bi-directional for receiving codes, data and addresses and transmitting output. The data bus is also bi-directional for receiving and transmitting data. One external chip enable pin and one external output enable pin are shared by the three memories to reduce the number of pins required for the single chip. Both NAND and NOR memories have dual read page buffers and dual write page buffers for Read-While-Load and Write-While-Program operations to accelerate the read and write operations respectively. A memory-mapped method is used to select different memories, status registers and dual read or write page buffers.
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