Low loss package for electronic device
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United States of America Patent
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Apr 3, 2012
Grant Date -
N/A
app pub date -
Dec 14, 2009
filing date -
Dec 14, 2009
priority date (Note) -
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Abstract
A package for one or more semiconductor die is described. A generally rectangular package includes two large terminals that occupy substantially the entire length of the package and provide low resistance connections. Additional connections may be provided preferably in a central portion of a short end of the package. BGA connections between the semiconductor die and the package substrate provide low impedance connections between the die and the package contacts. The package and connections facilitate current flow orthogonal to the longest package dimension maximizing conductor width and minimizing interconnection resistance.
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